HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 71

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Type
Arithmetic
operations
Instruction
DIVXS
CMP
NEG
EXTU
EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
Size *
B/W
B/W/L
B/W/L
W/L
W/L
B
—
—
L
1
Function
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits
remainder or 32 bits ÷ 16 bits
bit remainder.
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
Takes the two's complement (arithmetic complement) of
data in a general register.
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
@ERd – 0, 1
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
(EAs)
Performs signed multiplication on memory contents and
adds the result to the multiply-accumulate register. The
following operations can be performed:
16 bits
16 bits
0
Clears the multiply-accumulate register to zero.
Rs
Transfers data between a general register and a
multiply-accumulate register.
Rd ÷ Rs
0 – Rd
Rd (zero extension)
Rd (sign extension)
MAC
MAC, MAC
(EAd) + MAC
16 bits + 32 bits
16 bits + 42 bits
Rd
Rd
Rev. 5.00 Jan 10, 2006 page 45 of 1042
(<bit 7> of @ERd) *
Rd
Rd
Rd
MAC
32 bits, saturating
42 bits, non-saturating
16-bit quotient and 16-
8-bit quotient and 8-bit
2
REJ09B0275-0500
Section 2 CPU