HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 664

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 19 ROM (Preliminary)
19.5.3
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically
cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory block configuration is shown in table 19.4.
19.5.4
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is not set, even
though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block
can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2
combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and
EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be written with 0.
When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 19.4.
Rev. 5.00 Jan 10, 2006 page 638 of 1042
REJ09B0275-0500
Initial value:
Initial value:
Erase Block Register 1 (EBR1)
Erase Block Register 2 (EBR2)
R/W:
R/W:
Bit:
Bit:
EB7
R/W
R/W
—
7
0
7
0
EB6
R/W
R/W
—
6
0
6
0
R/W
R/W
EB5
—
5
0
5
0
R/W
R/W
EB4
—
4
0
4
0
EB11
R/W
R/W
EB3
3
0
3
0
EB10
R/W
R/W
EB2
2
0
2
0
R/W
R/W
EB1
EB9
1
0
1
0
R/W
R/W
EB0
EB8
0
0
0
0