HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 204

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Bus Controller
7.8
7.8.1
The H8S/2626 Group and H8S/2623 Group can release the external bus in response to a bus
request from an external device. In the external bus released state, the internal bus master
continues to operate as long as there is no external access.
If an internal bus master wants to make an external access in the external bus released state, it can
issue a bus request off-chip.
7.8.2
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2626 Group or
H8S/2623 Group. When the BREQ pin is sampled, at the prescribed timing the BACK pin is
driven low, and the address bus, data bus, and bus control signals are placed in the high-
impedance state, establishing the external bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped.
If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external
access in the external bus released state, the BREQO pin is driven low and a request can be made
off-chip to drop the bus request.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and internal bus master external access occur simultaneously, the
order of priority is as follows:
Rev. 5.00 Jan 10, 2006 page 178 of 1042
REJ09B0275-0500
Bus Release
Overview
Operation
(High) External bus release > Internal bus master external access (Low)