HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 832

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix A Instruction Set
A.4
The tables in this section can be used to calculate the number of states required for instruction
execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. Table A.4 indicates the number of states required for
each cycle. The number of states required for execution of an instruction can be calculated from
these two tables as follows:
Examples: Advanced mode, program code and stack located in external memory, on-chip
supporting modules accessed in two states with 8-bit bus width, external devices accessed in three
states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
2. JSR @@30
Rev. 5.00 Jan 10, 2006 page 806 of 1042
REJ09B0275-0500
From table A.5:
From table A.4:
Number of states required for execution = 2
From table A.5:
From table A.4:
Number of states required for execution = 2
Execution states = I
I = L = 2, J = K = M = N = 0
S
I = J = K = 2, L = M = N = 0
S
Number of States Required for Instruction Execution
I
I
= 4, S
= S
J
= S
L
K
= 2
= 4
S
I
+ J S
J
+ K
S
K
+ L
4 + 2
4 + 2
S
L
+ M
2 = 12
4 + 2
S
M
4 = 24
+ N
S
N