HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 761

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

21B.8.2 Exiting Watch Mode
Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at
the RES, or STBY pins.
(1) Exiting Watch Mode by Interrupts
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit
= 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits
and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed.
In the case of IRQ0 to IRQ5 interrupts, no transition is made from watch mode if the
corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal
supporting modules, the interrupt enable register has been set to disable the reception of that
interrupt, or is masked by the CPU.
See section 21B.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode,
for how to set the oscillation stabilization time when making a transition from watch mode to
high-speed mode.
(2) Exiting Watch Mode by RES
For exiting watch mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2,
Clearing Software Standby Mode.
(3) Exiting Watch Mode by STBY
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
21B.8.3 Notes
(1) I/O Port Status
The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the
address bus and bus control signals continue to be output. Therefore, when a High level is output,
the current consumption is not diminished by the amount of current to support the High level
output.
(2) Current Consumption when Waiting for Oscillation Stabilization
The current consumption increases during stabilization of oscillation.
RES pins
RES
RES
STBY
STBY
STBY pin
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 735 of 1042
REJ09B0275-0500