HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 21

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3 Operation .......................................................................................................................... 560
15.4 CAN Bus Interface............................................................................................................ 585
15.5 Usage Notes ...................................................................................................................... 585
Section 16 A/D Converter
16.1 Overview........................................................................................................................... 589
16.2 Register Descriptions ........................................................................................................ 593
16.3 Interface to Bus Master ..................................................................................................... 599
16.4 Operation .......................................................................................................................... 600
16.5 Interrupts ........................................................................................................................... 606
16.6 Usage Notes ...................................................................................................................... 607
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
17.1 Overview........................................................................................................................... 613
15.2.15 Transmit Error Counter (TEC)............................................................................. 549
15.2.16 Unread Message Status Register (UMSR) ........................................................... 550
15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 551
15.2.18 Message Control (MC0 to MC15) ....................................................................... 553
15.2.19 Message Data (MD0 to MD15) ........................................................................... 557
15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 559
15.3.1 Hardware and Software Resets ............................................................................ 560
15.3.2 Initialization after Hardware Reset ...................................................................... 563
15.3.3 Transmit Mode..................................................................................................... 568
15.3.4 Receive Mode ...................................................................................................... 574
15.3.5 HCAN Sleep Mode .............................................................................................. 579
15.3.6 HCAN Halt Mode ................................................................................................ 582
15.3.7 Interrupt Interface ................................................................................................ 583
15.3.8 DTC Interface ...................................................................................................... 584
16.1.1 Features................................................................................................................ 589
16.1.2 Block Diagram ..................................................................................................... 590
16.1.3 Pin Configuration................................................................................................. 591
16.1.4 Register Configuration......................................................................................... 592
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 593
16.2.2 A/D Control/Status Register (ADCSR) ............................................................... 594
16.2.3 A/D Control Register (ADCR) ............................................................................ 597
16.2.4 Module Stop Control Register A (MSTPCRA) ................................................... 598
16.4.1 Single Mode (SCAN = 0) .................................................................................... 600
16.4.2 Scan Mode (SCAN = 1)....................................................................................... 602
16.4.3 Input Sampling and A/D Conversion Time ......................................................... 604
16.4.4 External Trigger Input Timing............................................................................. 605
17.1.1 Features................................................................................................................ 613
................................................................................................. 589
Rev. 5.00 Jan 10, 2006 page xix of xxiv
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