HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 546

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 Smart Card Interface
Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by
the SCI in receive mode and transmit mode as described below.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
Rev. 5.00 Jan 10, 2006 page 520 of 1042
REJ09B0275-0500
Retransfer operation when SCI is in receive mode
Figure 14.11 illustrates the retransfer operation when the SCI is in receive mode.
automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
If DTC data transfer by an RXI source is enabled, the contents of RDR can be read
automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared
to 0.
error signal transmission.
RDRF
PER
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 14.11 Retransfer Operation in SCI Receive Mode
nth transfer frame
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransferred frame
(DE)
[4]
[3]
Ds D0 D1 D2 D3 D4
Transfer
frame n+1