HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 128

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
Table 5.3
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
IPRM
Notes: 1. Reserved bits. These bits are always read as 1 and cannot be modified.
As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range
from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding
interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority
level, level 7, by setting H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority
levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt
mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if
the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to
the CPU.
Rev. 5.00 Jan 10, 2006 page 102 of 1042
REJ09B0275-0500
2. Valid only in the H8S/2626 Group.
Correspondence between Interrupt Sources and IPR Settings
6 to 4
IRQ0
IRQ2
IRQ3
— *
WDT0
PC break
TPU channel 0
TPU channel 2
TPU channel 4
— *
— *
SCI channel 1
HCAN
1
1
1
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC
— *
A/D converter, WDT1 *
TPU channel 1
TPU channel 3
TPU channel 5
— *
SCI channel 0
SCI channel 2
— *
1
1
1
2