HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 948

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Register
TIOR3L—Timer I/O Control Register 3L
Rev. 5.00 Jan 10, 2006 page 922 of 1042
REJ09B0275-0500
Bit
Initial value
Read/Write
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
:
:
:
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and /1 is used as the
TGR3D I/O control
0 0
1
IOD3
R/W
7
0
1 0 0
0
1
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
0 0
1 0
1 0
0 0 TGR3D
1 *
*
TCNT4 count clock, this setting is invalid and input capture is not generated.
this setting is invalid and input capture/output compare is not generated.
1
1
1
1
1
*
TGR3D
is output
compare
register
is input
capture
register
IOD2
R/W
TRG3C I/O control
6
0
0 0
1
1 0 0
0
1
*2
*2
0 0
1 0
1 0
0 0 TGR3C
1 *
*
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCD3 pin
Capture input
source is channel
4/count clock
IOD1
1
1
1
1
1
*
R/W
5
0
TGR3C
is output
compare
register
is input
capture
register
IOD0
R/W
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCC3 pin
Capture input
source is channel
4/count clock
4
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
H'FE83
IOC3
R/W
3
0
*1
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
IOC2
R/W
2
0
*: Don’t care
IOC1
R/W
1
0
*: Don’t care
IOC0
R/W
0
0
TPU3