HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 671

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be
a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 2,400,
4,800, 9,600 or 19,200 bps to operate the SCI properly.
Table 19.7 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI bit rate is possible. The boot program should be executed within this system
clock range.
Table 19.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Host Bit Rate
2,400 bps
4,800 bps
9,600 bps
19,200 bps
Possible
Start
bit
System Clock Frequency for Which Automatic Adjustment
of LSI Bit Rate is Possible
2 to 8 MHz
4 to 16 MHz
8 to 20 MHz
16 to 20 MHz
D0
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
Rev. 5.00 Jan 10, 2006 page 645 of 1042
D5
Section 19 ROM (Preliminary)
D6
D7
(1 or more bits)
REJ09B0275-0500
High period
Stop
bit