HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 1025

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

TCSR1—Timer Control/Status Register 1 *
Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access.
Bit
Initial value
Read/Write
1. Only 0 can be written to these bits (to clear these flags).
2. This register is not available, and must not be accessed, in the H8S/2623 Group.
R/(W)
Overflow flag
0
1
OVF
7
0
[Clearing]
(1) When 0 is written to TME bit;
(2) When 0 is written to OVF bit after reading TCSR when OVF=1.
[Setting]
When TCNT overflows (H'FF
When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.
*1
Timer mode select
0
1
WT/IT
Interval timer mode: Interval timer interrupt (WOVI) request sent to CPU
when overflow occurs at TCNT
Watchdog timer mode: Reset or NMI interrupt request sent to CPU when
overflow occurs at TCNT
R/W
6
0
Timer enable
0
1
Initializes TCNT to H’00 and disables the counting operation
TCNT performs counting operation
TME
R/W
Prescaler select
0
1
5
0
H'00).
TCNT counts the divided clock output by the ø-based prescaler
TCNT counts the divided clock output by the øSUB-based prescaler (PSS)
Reset or NMI
2
0
1
PSS
R/W
NMI interrupt request
Internal reset request
4
0
Clock select 2 to 0
Note: * The overflow cycle starts when TCNT starts counting from
PSS CKS2 CKS1 CKS0
0
1
H'FFA2
RST/NMI
Rev. 5.00 Jan 10, 2006 page 999 of 1042
H'00 and ends when an overflow occurs.
R/W
0
1
0
1
3
0
0
1
0
1
0
1
0
1
Appendix B Internal I/O Register
CKS2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
2
0
/2
/64
/128
/512
/2048
/8192
/32768
/131072
SUB/2
SUB/4
SUB/8
SUB/16
SUB/32
SUB/64
SUB/128
SUB/256
Clock
CKS1
R/W
1
0
(when SUB = 32.768 kHz)
REJ09B0275-0500
(when
Overflow cycle *
25.6 s
819.2 s
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
CKS0
R/W
= 20 MHz)
0
0
WDT1