HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 165

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.1
The H8S/2626 Group and H8S/2623 Group have an on-chip bus controller (BSC) that manages
the external address space divided into eight areas. The bus specifications, such as bus width and
number of access states, can be set independently for each area, enabling multiple memories to be
connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU and data transfer controller (DTC).
7.1.1
The features of the bus controller are listed below.
Manages external address space in area units
Basic bus interface
Burst ROM interface
Idle cycle insertion
Write buffer functions
Bus arbitration function
Other features
Manages the external space as 8 areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM interface can be set
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
Burst ROM interface can be set for area 0
Choice of 1- or 2-state burst access
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted in case of an external write cycle immediately after an
external read cycle
External write cycle and internal access can be executed in parallel
Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC
External bus release function
Features
Overview
Section 7 Bus Controller
Rev. 5.00 Jan 10, 2006 page 139 of 1042
Section 7 Bus Controller
REJ09B0275-0500