HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 152

IC H8S MCU FLASH 256K 100-QFP

HD64F2623FA20J

Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2623FA20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 5 Interrupt Controller
(2) Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 8.3.3, DTC Vector Table, for the respective
priorities.
(3) Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC
data transfer is performed first, followed by CPU interrupt exception handling.
Table 5.11 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERG in the DTC, and the DISEL bit of MRB
in the DTC.
Table 5.11 Interrupt Source Selection and Clearing Control
DTC
DTCE
0
1
Legend:
O: The relevant interrupt is used. The interrupt source is not cleared.
X : The relevant bit cannot be used.
* : Don’t care
(4) Notes on Use
SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the
prescribed register.
Rev. 5.00 Jan 10, 2006 page 126 of 1042
REJ09B0275-0500
: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
Settings
DISEL
*
0
1
Interrupt Source Selection/Clearing Control
DTC
X
O
CPU
X

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