HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 86

IC H8S MCU FLASH 256K 100-QFP

HD64F2623FA20J

Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2623FA20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 2 CPU
2.8
2.8.1
The CPU has five main processing states: the reset state, exception handling state, program
execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the
processing states. Figure 2.15 indicates the state transitions.
Rev. 5.00 Jan 10, 2006 page 60 of 1042
REJ09B0275-0500
Note: * The power-down state also includes a medium-speed mode, module stop mode,
Processing
states
Processing States
Overview
subactive mode, subsleep mode, and watch mode. Subclock functions (subactive
mode, subsleep mode, and watch mode) are not available in the H8S/2623 Group,
but are available in the H8S/2626 Group.
Exception-handling
Program execution
Bus-released state
Power-down state
Figure 2.14 Processing States
The CPU and all on-chip supporting modules have been
initialized and are stopped.
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
The CPU executes program instructions in sequence.
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
CPU operation is stopped
to conserve power. *
Reset state
state
state
Hardware standby
Software standby
Sleep mode
mode
mode

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