HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 956

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 26 LCD Controller (LCDC)
26.3.22 LCDC Memory Access Interval Number Register (LDLIRNR)
LDLIRNR controls the bus cycle interval when the LCDC reads VRAM. When LDLIRNR is set
to other than H′00, the LCDC does not access VRAM until the specified number of bus cycles
(accessing the external memory or on-chip registers) has been performed by the
CPU/DMAC/USBH. When LDLIRNR is set to H'00 (initial value), the LCDC accesses the
VRAM, the CPU/DMAC/USBH performs one bus cycle, and then the LCDC accessed VRAM.
Page 896 of 1414
Bit
15 to 8 ⎯
7 to 0
Bus cycle
CKIO
Bit Name
LIRN7 to
LIRN0
LCDC1 LCDC2
(When displaying routated image,
4/8/16/32 can be selected.)
16 bursts
LCDC3
Initial Value
All 0
All 0
...
LCDC16
R/W
R
R/W
The number of bus cycles other than LCDC is set to
CPU
LIRN7 to LIRN0. (1 to 255 bus cycles)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
VRAM Read Bus Cycle Interval
Specifies the number of the CPU/DMAC/USBH
bus cycles which can be performed during burst
bus cycles to read VRAM by LCDC.
H'00: one bus cycle
H'01: one bus cycle
H'FF: 255 bus cycles
CPU
:
...
CPU
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
LCDC1
Sep 21, 2010
...