HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 33

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview
Figure 1.1
Figure 1.2
Figure 1.3
Section 2 CPU
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Section 3 DSP Operating Unit
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Figure 3.9
Figure 3.10
Figure 3.11
Figure 3.12
Figure 3.13
Figure 3.14
Figure 3.15
Figure 3.16
Figure 3.17
Figure 3.18
Figure 3.19
Figure 3.20
Figure 3.21
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Block Diagram........................................................................................................ 10
Pin Assignments (PLBG0256GA-A (BP-256H/HV)) ............................................ 11
Pin Assignments (PLBG0256KA-A (BP-256C/CV))............................................. 12
Processing State Transitions ................................................................................... 38
Virtual Address to External Memory Space Mapping ............................................ 41
Register Configuration in Each Processing Mode .................................................. 44
General Registers.................................................................................................... 46
System Registers and Program Counter.................................................................. 47
Control Register Configuration............................................................................... 51
Data Format on Memory (Big Endian Mode)......................................................... 52
Data Format on Memory (Little Endian Mode)...................................................... 53
DSP Instruction Format .......................................................................................... 82
CPU Registers in DSP Mode .................................................................................. 84
DSP Register Configuration ................................................................................... 88
DSP Registers and Bus Connections .................................................................... 101
General Registers (DSP Mode)............................................................................. 104
Sample Parallel Instruction Program .................................................................... 119
Examples of Conditional Operations and Data Transfer Instructions................... 121
Data Formats......................................................................................................... 124
ALU Fixed-Point Arithmetic Operation Flow ...................................................... 125
Operation Sequence Example ............................................................................... 127
DC Bit Generation Examples in Carry or Borrow Mode...................................... 128
DC Bit Generation Examples in Negative Value Mode ....................................... 129
DC Bit Generation Examples in Overflow Mode ................................................. 129
ALU Integer Arithmetic Operation Flow.............................................................. 131
ALU Logical Operation Flow............................................................................... 133
Fixed-Point Multiply Operation Flow................................................................... 135
Arithmetic Shift Operation Flow .......................................................................... 137
Logical Shift Operation Flow ............................................................................... 139
PDMSB Operation Flow....................................................................................... 141
Rounding Operation Flow..................................................................................... 145
Definition of Rounding Operation ........................................................................ 145
Figures
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