HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 764

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 21 Serial I/O with FIFO (SIOF)
21.3.11 Transmit Data Assign Register (SITDAR)
SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a
frame (slot number).
Page 704 of 1414
Bit
2
1
0
Bit
15
14 to 12
Bit Name
BRDV2
BRDV1
BRDV0
Bit Name
TDLE
⎯
Initial
Value
0
0
0
Initial
Value
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Baud rate generator's Division Ratio Setting
Set the frequency division ratio for the output stage of the
baud rate generator.
000: Prescalar output × 1/2
001: Prescalar output × 1/4
010: Prescalar output × 1/8
011: Prescalar output × 1/16
100: Prescalar output × 1/32
101: Setting prohibited
110: Setting prohibited
111: Prescalar output × 1/1*
The final frequency division ratio of the baud rate
generator is determined by BRPS × BRDV (maximum
1/1024).
Note: * This setting is valid only when the BRPS4 to
Description
Transmit Left-Channel Data Enable
0: Disables left-channel data transmission
1: Enables left-channel data transmission
Reserved
These bits are always read as 0. The write value should
always be 0.
BRPS0 bits are set to B'00000.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010