HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 499

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(2)
There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB bits in the
channel control register (CHCR).
(a)
• Normal mode
• Intermittent mode 16 and intermittent mode 64
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
In cycle-steal normal mode, the bus mastership is given to another bus master after a one-
transfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from the other bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to the
other bus master. This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination.
Figure 10.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
⎯ Dual address mode
⎯ DREQ low level detection
In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. If the next
transfer request occurs after that, the DMAC gets the bus mastership from other bus master
after waiting for 16 or 64 clocks in Bφ count. The DMAC then transfers data of one unit and
returns the bus mastership to other bus master. These operations are repeated until the transfer
end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by
DMA transfer than cycle-steal normal mode.
When the DMAC gets again the bus mastership, DMA transfer can be postponed in case of
entry updating due to cache miss.
Bus Modes
Cycle-Steal Mode
Bus cycle
DREQ
Figure 10.9 DMA Transfer Example in Cycle-Steal Normal Mode
CPU
(Dual Address, DREQ Low Level Detection)
CPU
CPU
DMAC DMAC
Read/Write
Bus mastership returned to CPU once
CPU
Section 10 Direct Memory Access Controller (DMAC)
DMAC
Read/Write
DMAC
CPU
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