HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 424

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Section 9 Bus State Controller (BSC)
(5)
Burst Write
A burst write occurs in the following cases in this LSI.
1. Access size in writing is larger than data bus width.
2. Copyback of the cache
3. 16-byte transfer in DMAC (access to non-cacheable region)
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is
connected to a 32-bit data bus. The relationship between the access size and the number of bursts
is shown in table 9.18.
Figure 9.17 shows a timing chart for burst writes. In burst write, an ACTV command is output in
the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA
command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data
is output simultaneously with the write command. After the write command with the auto-
precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the
Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the
SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access
to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1
cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is
specified by the TRP1 and TRP0 bits in CS3WCR.
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R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010