HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 428

Manufacturer Part Number

HD6417720BP133BV

SH3-DSP, WITH USB AND LCDC, PB-F

Manufacturer

Renesas Electronics America

SuperH® SH7700r

Core Processor

Connectivity

FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

Section 9 Bus State Controller (BSC)

When bank active mode is set, if only accesses to the respective banks in the area 3 space are

considered, as long as accesses to the same row address continue, the operation starts with the

cycle in figure 9.19 or 9.22, followed by repetition of the cycle in figure 9.20 or 9.23. An access to

a different area during this time has no effect. If there is an access to a different row address in the

bank active state, after this is detected the bus cycle in figure 9.21 or 9.24 is executed instead of

that in figure 9.20 or 9.23. In bank active mode, too, all banks become inactive after a refresh

cycle or after the bus is released as the result of bus arbitration.

Page 368 of 1414

Figure 9.19 Burst Read Timing (No Auto-Precharge)

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

SH7720 Group, SH7721 Group

R01UH0083EJ0400 Rev. 4.00

Sep 21, 2010