HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 486

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Direct Memory Access Controller (DMAC)
10.4.2
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices or on-chip peripheral modules that are neither the
source nor the destination. Transfers can be requested in three modes: auto request, external
request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0
bits in CHCR0 to CHCR3, and DMARS0 to DMARS2.
(1)
When there is no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal
internally. When the DE bits in CHCR and the DME bit in DMAOR are set to 1, the transfer
begins so long as the AE and NMIF bits in DMAOR are all 0.
(2)
In this mode, a transfer is performed at the request signals (DREQ0 and DREQ1) of an external
device. This mode is valid only in channel 0 and channel 1. Choose one of the modes shown in
table 10.3 according to the application system. When this mode is selected, if the DMA transfer is
enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at
the DREQ input.
Table 10.3 Selecting External Request Modes with RS Bits
Page 426 of 1414
RS3
0
Auto-Request Mode
External Request Mode
RS2
0
DMA Transfer Requests
RS1
0
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Source
Any
External memory,
memory-mapped
external device
External device with
DACK
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Destination
Any
External device with
DACK
External memory,
memory-mapped
external device
Sep 21, 2010