HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 523

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
11.4
The CPG has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and access size of these registers.
• Frequency control register (FRQCR)
• USBH/USBF clock control register (UCLKCR)
11.4.1
The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify
whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1,
and the frequency division ratio of the internal clock and the peripheral clock.
Only word access can be used on the FRQCR register. FRQCR is initialized by a power-on reset,
but not initialized by a power-on reset at the WDT overflow. FRQCR retains its value in a manual
reset and in standby mode.
The write values to bits 14, 13, 11, 10, 7, 6, and 3 should always be 0.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15
14, 13 ⎯
Bit Name
PLL2EN
Register Descriptions
Frequency Control Register (FRQCR)
Initial
Value
0
All 0
R/W
R/W
R
Description
PLL2 Enable
PLL2EN specifies whether make the PLL circuit 2 ON in
clock operating mode 7.
PLL circuit 2 is ON in clock operating modes other than
mode 7 regardless of the PLL2EN setting.
0: PLL circuit 2 is OFF
1: PLL circuit 2 is ON
Reserved
These bits are always read as 0. The write value should
always be 0.
Section 11 Clock Pulse Generator (CPG)
Page 463 of 1414