HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 535

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
12.2.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
• Writing to WTCNT and WTCSR
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
2
1
0
These registers must be written by a word transfer instruction. They cannot be written by a
byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A
and transfer the lower byte as the write data, as shown in figure 12.3. When writing to
WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer
procedure writes the lower byte data to WTCNT or WTCSR.
Bit Name
CKS2
CKS1
CKS0
Notes on Register Access
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Clock Select 2 to 0
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is shown
inside the parenthesis in the table is the value when the
peripheral clock (Pφ) is 15 MHz.
000: Pφ (17 μs)
001: Pφ /4 (68 μs)
010: Pφ /16 (273 μs)
011: Pφ /32 (546 μs)
100: Pφ /64 (1.09 ms)
101: Pφ /256 (4.36 ms)
110: Pφ /1024 (17.48 ms)
111: Pφ /4096 (69.91 ms)
Note: If bits CKS2 to CKS0 are modified when the WDT
is operating, the up-count may not be performed
correctly. Ensure that these bits are modified only
when the WDT is not operating.
Section 12 Watchdog Timer (WDT)
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