HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 919

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
25.9
25.9.1
The following points should be noted on the EP0s data register (EPDR0s) in which reception of 8-
byte setup data is performed.
1. Since the setup command must be received in the USB, writing from the USB bus side is prior
2. EPDR0s must be read in 8-byte units. If reading is suspended while it is in progress, data
25.9.2
When the USB cable is disconnected during communication, data which is receiving or
transmitting may remain in the FIFO. Therefore the FIFO must be cleared immediately after
connecting the USB cable again.
Note that the FIFO in which data is receiving from the host or transmitting to the host must not be
cleared.
25.9.3
The following points should be noted when the data register of the USBF is read from or written
to.
(1)
The receive data register must not read data which is more than valid receive data bytes. That is,
data which is more than bytes indicated in the receive data size register must not be read. In case
of the receive data register which has the dual FIFO buffer, the maximum number of data which
can be read in a single time is maximum packet size. Write 1 to TRG after data in the current valid
buffer is read. This writing switches the FIFO buffer. Then, the new number of bytes is reflected
in the receive data size and the next data can be read.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
to reading from the CPU side. While the CPU reads data after completion of reception and
reception of the next setup command is started, reading from the CPU side is forcibly invalid.
Therefore a value to be read after starting reception is undefined.
received in the next setup cannot be read successfully.
Receive Data Register
Usage Notes
Setup Data Reception
FIFO Clear
Overreading/Overwriting of Data Register
Section 25 USB Function Controller (USBF)
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