HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 781

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
21.4.7
(1)
Figure 21.9 shows an example of settings and operation for master mode transmission.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Transmission in Master Mode
Transmit and Receive Procedures
Figure 21.9 Example of Transmit Operation in Master Mode
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the
10
11
12
No.
1
2
3
4
5
6
7
8
9
TXE bit should be set to 1.
SIRDAR, SICDAR, and SIFCTR
Transmit SITDR from SIOFTXD
Set the MSSEL bit in SISCR to 1
Set the SCKE bit in SICTR to 1
synchronously with SIOFSYNC
Clear the TXE bit in SICTR to 0
Reset the master clock source
Set SIMDR, SISCR, SITDAR,
Set the FSE bit in SICTR to 0
and BPRS=00000 in SISCR
Set the FSE and TXE bits
Start the setting FSE=0,
and baud rate in SISCR
to the TXRST in SISCR
Start SIOFSCK output
Add pulse (0→1→0)
TXE=0 and other bit.
transmit mode?
Set BRDV=111
Change other
in SICTR to 1
TDREQ = 1?
Set SITDR
Flow Chart
Transfer
ended?
Start
Yes
Yes
Yes
No
No
No
End
Set the start for frame synchronous
signal output and enable
transmission
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set operation start for baud rate
generator
Set transmit data
Set to disable transmission
Synchronize this LSI internal
frame with FSE=0 if restarting
transmit later.
Execute internal initialization
of the bit rate generator
if restarting transmit later.
'No' requires further setting
if transmission is not restarted
(No).
When returning to the same
transmit mode from here,
go back to No.4, FSE setting,
on this flowchart.
Go to "Start" on each flowchart.
SIOF Settings
Output serial clock
Output frame synchronous
signal and issue transmit
transfer request*
End transmission
Transmit
Section 21 Serial I/O with FIFO (SIOF)
SIOF Operation
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