HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1279

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
Table 36.1 Pin Configuration
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Pin Name
TCK
TMS
TRST
TDI
TDO
ASEMD0
ASEBRKAK
AUDSYNC
AUDATA3 to
AUDATA0
AUDCK
I/O
Input
Input
Input
Input
Output
Input
Output
Description
Serial Data Input/Output Clock Pin
Data is serially supplied to the H-UDI from the data input pin (TDI), and
output from the data output pin (TDO), in synchronization with this
clock.
Mode Select Input Pin
The state of the TAP control circuit is determined by changing this
signal in synchronization with TCK. The protocol supports the JTAG
standard (IEEE Std.1149.1).
Reset Input Pin
Input is accepted asynchronously with respect to TCK, and when low,
the H-UDI is reset. TRST must be low for a constant period when power
is turned on regardless of using the H-UDI function. This is different
from the JTAG standard.
See section 36.4.2, Reset Configuration, for more information.
Serial Data Input Pin
Data transfer to the H-UDI is executed by changing this signal in
synchronization with TCK.
Serial Data Output Pin
Data read from the H-UDI is executed by reading this pin in
synchronization with TCK. The data output timing depends on the
command type set in the SDIR. See section 36.4.3, TDO Output
Timing, for more information.
ASE Mode Select Pin
If a low level is input at the ASEMD0 pin while the RESETP pin is
asserted, ASE mode is entered; if a high level is input, normal mode is
entered. When the ASEMD0 pin is used by the user system alone
without using the emulator and H-UDI, fix the ASEMD0 pin high. In ASE
mode, dedicated emulator function can be used. The input level at the
ASEMD0 pin should be held for at least one cycle after RESETP
negation.
Dedicated Emulator Pin
Section 36 User Debugging Interface (H-UDI)
Page 1219 of 1414