HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 190

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 DSP Operating Unit
(5)
The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data
(signed) as the result of compare operation PCMP. The PCMP operation should be executed
before executing the conditional operation under this condition mode. This mode is similar to the
Negative Value Mode described before, because the result of a compare operation is a positive
value if the source 1 data is greater than the source 2 data. However, the signed bit of the result
shows a negative value if the compare operation yields a result beyond the range of the destination
operand, including the guard-bit parts (called “Over-range”), even though the source 1 data is
greater than the source 2 data. The DC bit is updated concerning this type of special case in this
condition mode. The equation below shows the definition of getting this condition:
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of the CMP/GT operation of the CPU instruction.
(6)
The DC bit indicates whether the source 1 data (signed) is greater than or equal to the source 2
data (signed) as the result of compare operation PCMP. This mode is similar to the Signed Greater
Than Mode described before but the equal case is also included in this mode. The equation below
shows the definition of getting this condition:
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of a CMP/GE operation of the CPU instruction.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
Note: The DC bit is always updated as the carry flag for ‘PADDC’ and is always updated as the
• Overflow Protection
Page 130 of 1414
The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See
section 3.5.11, Overflow Protection, for details.
Signed Greater Than Mode: CS[2:0] = B'100
Signed Greater Than or Equal Mode: CS[2:0] = B'101
carry/borrow flag for ‘PSUBC’ regardless of the CS[2:0] state.
DC = ~ {(Negative ^ Over-range) | Zero}
DC = ~ (Negative ^ Over-range)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010