HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 700

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Serial Communication Interface with FIFO (SCIF)
(4)
An example with a sampling rate 1/16 is given. The SCIF operates on a base clock with a
frequency of 8 times the transfer rate. In reception, the SCIF synchronizes internally with the fall
of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the
eighth base clock pulse. The timing is shown in figure 18.17.
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
Equation 1:
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Page 640 of 1414
Receive Data Sampling Timing and Receive Margin
M = 0.5 −
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
M = (0.5 – 1/(2 × 16)) × 100%
Figure 18.17 Receive Data Sampling Timing in Asynchronous Mode
= 46.875% ...................................................................................................... (2)
Base clock
data (RxD)
Synchro-
sampling
sampling
Receive
nization
timing
timing
Data
2N
1
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
− (L − 0.5) F −
Start bit
8 clocks
16 clocks
−7.5 clocks
D − 0.5
N
(1 + F) × 100%
+7.5 clocks
D0
........................ (1)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
D1
Sep 21, 2010