HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 540

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Power-Down Modes
Table 13.1 shows the transition conditions for entering the modes from the program execution
state, as well as the CPU and peripheral module states in each mode and the procedures for
canceling each mode.
Table 13.1 States of Power-Down Modes
Note:
13.1.2
Resetting occurs when power is supplied, and when execution is started again from an initialized
state. There are two types of reset: A power-on reset and a manual reset. In a power-on reset, all
processing in execution is suspended, all unprocessed events are canceled, and reset processing
starts immediately. On the other hand, processing to retain the contents of external memory is
continued in a manual reset. The conditions for generating power-on and manual resets are as
follows.
Page 480 of 1414
Mode
Sleep
mode
Software
Standby
mode
Module
standby
function
Hardware
standby
mode
* The RTC operates when the START bit in RCR2 is set to 1. For details, see section 17,
Reset
Transition
Conditions
Execute SLEEP
instruction with
STBY bit in STBCR
cleared to 0
Execute SLEEP
instruction with
STBY bit in STBCR
set to 1
Set MSTP bit in
STBCR to 1
Set CA pin to low
Realtime Clock (RTC).
CPG
Runs
Halts
Runs
Halts
CPU
Halts
Halts
Runs/
halts
Halts
CPU
Reg-
ister
Held
Held
Held
Held
On-Chip
Memory
Halts
(contents
remained)
Halts
(contents
remained)
Specified
module halts
(contents
remained)
Held
State
On-Chip
Periphera
l Modules
Run
Halt*
Specified
module
halts
Halt*
External
Memory
Auto-
refreshing
Self-
refreshing
Auto-
refreshing
Self-
refreshing
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Canceling
Procedure
•
•
•
•
•
•
•
(NMI, IRQ
(edge
detection),
RTC, TMU,
PINT
MSTP bit to
0
reset
reset
Interrupt
Reset
Interrupt
Reset
Clear
Power-on
Power-on
Sep 21, 2010