HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 114

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
2.5
2.5.1
(1)
All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the
sequential pipeline, almost all instructions can be executed in one cycle. All data items are handles
in longword (32 bits). Memory can be accessed in byte, word, or longword. In this case, Memory
byte or word data is sign-extended and operated on as longword data. Immediate data is sign-
extended to longword size for arithmetic operations (MOV, ADD, and CMP/EQ instructions) or
zero-extended to longword size for logical operations (TST, AND, OR, and XOR instructions).
(2)
Basic operations are executed between registers. In operations involving memory, data is first
loaded into a register (load/store architecture). However, bit manipulation instructions such as
AND are executed directly on memory.
(3)
Unconditional branch instructions are executed as delayed branches. With a delayed branch
instruction, the branch is made after execution of the instruction (called the slot instruction)
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made.
This LSI supports two types of conditional branch instructions: delayed branch instruction or
normal branch instruction.
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Example:
the
Instruction Length
Load/Store Architecture
Delayed Branching
Features of CPU Core Instructions
Instruction Execution Method
BRA
ADD
TARGET
R1, R0
; ADD is executed before branching to
TARGET
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010