HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 856

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 24 USB Host Controller (USBH)
Page 796 of 1414
Bit
2
1
Bit Name
PSS
PES
Initial
Value
0
0
R/W
R/W
R/W
Description
(Read) Port Suspend Status
This bit indicates that the port is suspended or during the
resume sequence. Writing SetSuspendState sets this bit
and setting PSSC clears this bit at the end of the resume
interval. If the CCS bit is cleared, this bit cannot be set.
When the PRSC bit is set upon completion of the port
reset or HC is placed in the UsbResume state, this bit is
cleared. If an upstream resume is in progress, it is
transmitted to the host controller.
0: Port is not suspended
1: Port is selectively suspended
(Write) Set Port Suspend
Writing a 1 sets PortSuspendStatus. Writing a 0 has no
effect.
In addition, when the CCS bit is cleared, the PSS bit is not
set by this writing. Instead, the CSC bit is set. This reports
the suspended state of the power disconnection to the
driver.
(Read) Port Enable Status
This bit indicates whether the port is enabled or disabled.
The root hub clears this bit when the over-current
condition and an operational bus error such as disconnect
event, power-off switch, or babble is detected. The PESC
is set by this change. This bit is set by writing
SetPortEnable and cleared by writing ClearPortEnable.
This bit cannot be set when the CCS bit is cleared. In
addition, this bit is set upon completion of the port reset by
which the PRSCtatusChange is set, or uponcompletion of
the port suspend by which the PSSC is set.
0: Port disabled
1: Port enabled
(Write) Set Port Enable
Writing a 1 sets the PES bit. Writing a 0 has no effect.
If the CCS bit is cleared, this writing does not set the PES
bit, instead, sets the CS. This reports the driver that the
power disconnection port has been tried to be enabled.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010