HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 467

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
This LSI includes the direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
10.1
• Six channels (two channels can receive an external request)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), and 16 bytes
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode or single address mode can be selected.
• Transfer requests:
• Selectable bus modes:
• Selectable channel priority levels:
• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the
• External request detection: There are following four types of DREQ input detection.
• Transfer request acknowledge signal:
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
(longword × 4)
External request, on-chip peripheral module request, or auto request can be selected.
The following modules can issue an on-chip peripheral module request.
⎯ SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, ADC, and
Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
The channel priority levels are selectable between fixed mode and round-robin mode.
specified counts.
⎯ Low level detection
⎯ High level detection
⎯ Rising edge detection
⎯ Falling edge detection
Active levels for DACK and TEND can be set independently.
Section 10 Direct Memory Access Controller (DMAC)
SDHI
Features
Section 10 Direct Memory Access Controller (DMAC)
DMAS301A_010020030200
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