HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 859

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
24.4.2
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of USB
Host Controller must be aligned so that each Dword corresponds to the long-word boundary
(addresses 4n to 4n + 3) of the memory.
24.5
24.5.1
The transferred data is stored in shared system memory with CPU. The data alignment in system
memory are restricted depends on SDRAM specification which is used as system memory.
In above figure, transfer data 1 and 3 are able to be read or written by USB Host Controller. But
transfer data 2 are possibly unable to be read or written by USB Host controller. Any data, which
have possibility to be accessed by USB Host Controller, must be aligned in SDRAM not to cross
row address alignment.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Storage Format of the Descriptor
Data Alignment Restriction of USB Host Controller
Restriction on the Line Boundary of the Synchronous DRAM
DRAM
Row address
Row address
Row address
n
n+1
n+2
Memory area
(2)
(3)
Section 24 USB Host Controller (USBH)
(1)
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