HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1126

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 MultiMediaCard Interface (MMCIF)
(5)
Flash memory operation commands include a number of commands involving read data. Such
commands confirm the card status by the command argument and command response, and receive
card information and flash memory data from the DAT pin.
For multiblock transfer, there are two methods. One is the open-ended method in which the
instruction for continuing/suspending the command sequence is made by suspending the transfer
for every block. Another one is the pre-defined method in which the transfer is performed after
setting the number of blocks to be transferred.
The command sequence is suspended when FIFO is full between the block transfers. When the
command sequence is suspended, data in the receive data FIFO is processed, if necessary, and the
command sequence is then continued.
Figures 31.7 to 31.10 show the examples of the command sequence for commands with read data.
Figures 31.11 to 31.14 show the operational flowcharts for commands with read data.
• Settings needed to issue a command are made. FIFO is cleared.
• The START bit in CMDSTRT is set to 1 to start command transmission.
• Command transmission complete can be confirmed by the command output end interrupt
• A command response is received from the MMC.
• If the MMC does not return the command response, the command response is detected by the
• Read data from the MMC is received.
• The suspension inter-blocks in multiblock transfer and suspension according to the FIFO full
• The end of the command sequence is detected by polling the BUSY flag in CSTR or by the
• When the CRC error (CRCERI) or command timeout error (CTERI) occurs during command
• When the CRC error (CRCERI) or data timeout error (DTERI) occurs during the read data
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(CMDI).
command timeout error (CTERI).
are detected by the data transfer end interrupt (DTI) and FIFO full interrupt (FFI), respectively.
To continue the command sequence, the RD_CONTI bit in OPCR should be set to 1. To end
the command sequence, the CMDOFF bit in OPCR should be set to 1, and the CMD12 should
be issued. Note that the CMD12 is not required other than when the sequence is suspended in
pre-defined multiblock transfer.
data transfer end flag (DTI) or the multiblock transfer (pre-defined) end flag (BTI).
response reception, write 1 to the CMDOFF bit.
reception, write 1 to the CMDOFF bit to clear the FIFO.
Commands with Read Data
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010