HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 504

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Direct Memory Access Controller (DMAC)
10.4.5
(1)
When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9,
Bus State Controller (BSC).
(2)
Figures 10.13, 10.14, 10.15, and 10.16 show the sample timing of the DREQ input in each bus
mode, respectively.
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Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Number of Bus Cycle States
DREQ Pin Sampling Timing
Number of Bus Cycle States and DREQ Pin Sampling Timing
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
1st acceptance
CPU
Non-sensitive period
CPU
DMAC
Acceptance started
2nd acceptance
CPU
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010