HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 513

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
10.5.3
1. Before making a transition to standby mode, either wait until DMA transfer finishes or
2. If an on-chip peripheral module whose clock supply is to be stopped by the module standby
3. Do not write to SAR, DAR, DMATCR, or DMARS during DMA transfer.
Concerning Above Notes 1 and 2:
DMA transfer end can be confirmed by checking whether the TE bit in CHCR is set to 1.
To suspend DMA transfer, clear the DE bit in CHCR to 0.
4. When reading these following flag bits while they are just setting to 1, the read out value of the
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
suspend DMA transfer.
function is performing DMA transfer, either wait until DMA transfer finishes or suspend DMA
transfer before making a transition to module standby mode.
corresponding flag is 0, but the internal state of this operation may become same as read out 1.
If writing 0 to the corresponding flag after this case, it is equivalent to write 0 after reading the
corresponding flag is 1, as a result, the corresponding flag is cleared to 0 unintentionally.
(1) DMA Channel Control Registers (CHCR_0 to CHCR_5) TE bit.
(2) DMA Operation Register (DMAOR) AE bit and NMIF bit.
When using corresponding flag, not to clear the flag unintentionally, it is necessary to read and
write by the following procedure.
When writing register that has the corresponding flags, write 1 to the flag bit except clearing
the flag explicitly.
Clearing the corresponding flag explicitly, write 0 to the flag bit after reading out 1. Writing 1
to the corresponding bit does not affect the value of the flag.
Note that, when not using corresponding flag, it is no problem to write always 0 (Clearing the
corresponding flag explicitly, write 0 to the flag bit after reading out 1).
Other Notes
Section 10 Direct Memory Access Controller (DMAC)
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