HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 371

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(2)
• CS0WCR
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
5 to 2
1
0
Bit
31 to 21 ⎯
20
19, 18
Burst ROM (Clock Asynchronous)
Bit Name
BEN
⎯
Bit Name
⎯
HW1
HW0
Initial
Value
All 0
0
All 0
Initial
Value
All 0
0
0
R/W Description
R
R/W Burst Enable Specification
R
R/W
R
R/W
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
Enables or disables 8-burst access for a 16-bit bus width or
16-burst access for an 8-bit bus width during 16-byte access.
If this bit is set to 1, 2-burst access is performed four times
when the bus width is 16 bits and 4-burst access is
performed four times when the bus width is 8 bits.
To use a device that does not support 8-burst access or 16-
burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-burst
1: Disables 8-burst access for a 16-bit bus width and 16-burst
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
access for an 8-bit bus width.
access for an 8-bit bus width.
Section 9 Bus State Controller (BSC)
Page 311 of 1414