HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 559

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
SH7720 Group, SH7721 Group
13.8.3
Figures 13.10 and 13.11 show signal timings in hardware standby mode. Since the signal on the
CA pin is sampled at the timing of EXTAL_RTC, clock should be input to the EXTAL_RTC pin
when hardware standby mode is entered. In hardware standby mode, the CA pin must be kept low.
The clock oscillation starts if the CA pin is pulled high after the RESETP pin is brought low.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Figure 13.10 Hardware Standby Mode Timing (CA is pulled low in normal operation)
CA
STATUS
Hardware Standby Mode Timing
CKIO
RESETP
Notes: 1. reset : HH (STATUS1 = High, STATUS0 = High)
2. standby : LHLH (STATUS1 = Low, STATUS0 = High)
3. normal : LL (STATUS1 = Low, STATUS0 = Low)
4. Bcyc : Bus clock cycle
normal*
3
standby*
2
0 to 10 Bcyc
Undefined
Section 13 Power-Down Modes
reset*
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