HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 236

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Memory Management Unit (MMU)
4.3
4.3.1
The TLB caches address translation table information located in the external memory. The address
translation table stores the virtual page number and the corresponding physical number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 4.6 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 4.7 shows the configuration of virtual
addresses and TLB entries.
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Entry 0
Entry 1
Entry 31
TLB Functions
Configuration of the TLB
VPN(31 to 17)
Address array
VPN(11 to 10)
Figure 4.6 Overall Configuration of the TLB
Way 0 to 3
ASID(7 to 0)
V
Entry 0
Entry 1
Entry 31
PPN(28 to 10)PR(1 to 0) SZ
SH7720 Group, SH7721 Group
Data array
R01UH0083EJ0400 Rev. 4.00
Way 0 to 3
C
Sep 21, 2010
D SH