HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 232

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Memory Management Unit (MMU)
information are registered in the TLB. After returning from the handler, the instruction that caused
the TLB miss is re-executed. When the MMU is enabled, address translation information that
results in a physical address space of H'2000 0000 to H'FFFF FFFF should not be registered in the
TLB.
When the MMU is disabled, masking the upper three bits of the virtual address to 0s creates the
address in the corresponding physical address space. Since this LSI supports 29-bit address space
as physical address space, the upper three bits of the virtual address are ignored as shadow areas.
For details, refer to section 9, Bus State Controller (BSC). For example, address H'0000 1000 in
the P0 area, address H'8000 1000 in the P1 area, address H'A000 1000 in the P2 area, and address
H'C000 1000 in the P3 area are all mapped to the same physical memory. If these addresses are
accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the
continuity of addresses stored in the address array of the cache.
(4)
There are two virtual memory modes: single virtual memory mode and multiple virtual memory
mode. In single virtual memory mode, multiple processes run in parallel using the virtual address
space exclusively and the physical address corresponding to a given virtual address is specified
uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the virtual
address space, so a given virtual address may be translated into different physical addresses
depending on the process. By the value set to the MMU control register (MMUCR), either single
or multiple virtual mode is selected.
In terms of operation, the only difference between single virtual memory mode and multiple
virtual memory mode is in the TLB address comparison method (see section 4.3.3, TLB Address
Comparison).
(5)
In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate
between processes running in parallel and sharing virtual address space. The ASID is eight bits in
length and can be set by software setting of the ASID of the currently running process in page
table entry register high (PTEH) within the MMU. When the process is switched using the ASID,
the TLB does not have to be purged.
In single virtual memory mode, the ASID is used to provide memory protection for processes
running simultaneously and using the virtual address space exclusively (see section 4.3.3, TLB
Address Comparison).
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Single Virtual Memory Mode and Multiple Virtual Memory Mode
Address Space Identifier (ASID)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010