HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 125

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Type
Branch
instructions
System
control
instructions
Total:
Kinds of
Instruction
9
15
68
Op Code
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
CLRMAC
CLRS
CLRT
LDC
LDS
LDTLB
NOP
PREF
RTE
SETS
SETT
SLEEP
STC
STS
TRAPA
Function
Conditional branch, delayed conditional
branch (T = 0)
Conditional branch, delayed conditional
branch (T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
MAC register clear
S bit clear
T bit clear
Load into control register
Load into system register
PTEH/PTEL load into TLB
No operation
Data prefetch to cache
Return from exception handling
S bit setting
T bit setting
Transition to power-down mode
Store from control register
Store from system register
Trap exception handling
Number of
Instructions
11
75
188
Page 65 of 1414
Section 2 CPU