HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 890

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 USB Function Controller (USBF)
25.3.36 Control Register 0 (CTLR0)
CTLR0 sets functions of ASCE, PWMD, RSME, and RWUP.
Page 830 of 1414
Bit
7 to 5
4
3
2
1
0
Bit
name
c
RWUPS
RSME
⎯
ASCE
⎯
Initial
value
All 0
0
0
0
0
0
R/W
R
R
R
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Remote Wakeup Status
Status bit to indicate that the remote wakeup from the
host is enabled/disabled. Indicates 0 when the remote
wakeup is disabled with Device Remote Wakeup by the
Set Feature/Clear Feature request and indicates 1 when
it is enabled.
Resume Enable
Bit to clear the suspend state (performs the remote
wakeup)
When this bit is written to 1, a resume register is set.
When this bit will be used, be sure to hold to 1 for one
clock or more at 12 MHz in minimum and then clear to 0
again.
Reserved
This bit is always read as 0. The write value should
always be 0.
Automatic Stall Clear Enable
When this bit is set to 1, the stall handshake is returned
to the host and the stall setting bit (EPSTLR/EPXSTL) of
the returned endpoint is automatically cleared. Control in
a unit of endpoint is disabled as this bit is common for all
endpoints. When this bit is set to 0, be sure to clear the
stall setting bit of each endpoint by using software.
This bit should be set to 1 before each stall bit in EPSTL
is set to 1.
Reserved
This bit is always read as 0. The write value should
always be 0.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010