HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 272

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Cache
5.4.3
(1)
Specific cache entries can be invalidated by writing 0 to the entry’s V bit in the memory-mapped
cache access. When the A bit is 1, the tag address specified by the write data is compared to the
tag address within the cache selected by the entry address, and a match is found, the entry is
written back if the entry’s U bit is 1 and the V bit and U bit specified by the write data are written.
If no match is found, there is no operation. In the example shown below, R0 specifies the write
data and R1 specifies the address.
(2)
To read the data field of a specific entry is enabled by the memory-mapped cache access. The
longword indicated in the data field of the data array in figure 5.4 is read into the register. In the
example shown below, R0 specifies the address and R1 shows what is read.
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; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'00001000, A=1
;
MOV.L R0,@R1
; R0=H'F100 004C; data array access, entry=B'00000100
; Way = 0, longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
Invalidating Specific Entries
Reading the Data of a Specific Entry
Usage Examples
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010