HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 731

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
20.4.6
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched
internally. Figure 20.16 shows a block diagram of the noise canceller circuit.
The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the peripheral clock, but is not passed forward to the next circuit unless
the outputs of both latches agree. If they do not agree, the previous value is held.
20.4.7
Flowcharts in respective modes that use the I
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
SCL or SDA
input signal
Sampling
clock
Noise Canceller
Example of Use
Figure 20.13 Block Diagram of Noise Conceller
Peripheral clock
Sampling clock
D
period
Latch
C
Q
D
2
C bus interface are shown in figures 20.17 to 20.20.
Latch
C
Q
March detector
Section 20 I
SCL or SDA
Internal
2
signal
C Bus Interface (IIC)
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