HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 916

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 USB Function Controller (USBF)
25.8
25.8.1
This section describes stall operations in this module. There are two cases in which the USB
function controller stall function is used:
• When the application forcibly stalls an endpoint for some reason
• When a stall is performed automatically within the USB function controller due to a USB
The USB function controller has internal status bits that hold the status (stall or non-stall) of each
endpoint. When a transaction is sent from the host, the module references these internal status bits
and determines whether to return a stall to the host. These bits cannot be cleared by the
application; they must be cleared with a Clear Feature command from the host.
However, the internal status bit to EP0 is automatically cleared only when the setup command is
received.
25.8.2
The application uses the EPSTL register to issue a stall request for the USB function controller.
When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (1-
1 in figure 25.16). The internal status bits are not changed at this time. When a transaction is sent
from the host for the endpoint for which the EPSTL bit was set, the USB function controller
references the internal status bit, and if this is not set, references the corresponding bit in EPSTL
(1-2 in figure 25.16). If the corresponding bit in USBEPSTL is set, the USB function controller
sets the internal status bit and returns a stall handshake to the host (1-3 in figure 25.16). In this
time, if the CTLR/ASCE bit is set to 1, the corresponding bit in EPSTL is automatically cleared to
0 and a stall handshake is returned to the host (1-4 in figure 25.16). If the corresponding bit in
EPSTL is not set, the internal status bit is not changed and the transaction is accepted.
Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the
host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature
command (3-1 in figure 25.16), the USB function controller continues to return a stall handshake
while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed
for the corresponding endpoint (1-2 in figure 25.16). To clear a stall, therefore, it is necessary for
the corresponding bit in EPSTL to be cleared automatically when a stall is returned from the USB
controller while the CTLR/ASCE bit is set to 1, or to be cleared by the application, and also for
the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure
25.16).
Page 856 of 1414
specification violation
Stall Operations
Overview
Forcible Stall by Application
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010