HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 126

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
Page 66 of 1414
Instruction
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement
OP:
Sz:
SRC:
DEST: Destination
Destination register
Operation code
Size
Source
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
a.
b.
instruction execution states will be increased in cases such as the following:
When there is a conflict between an instruction fetch and a data access
When the destination register of a load instruction (memory → register) is also
used by the following instruction
Instruction Code
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement *
2
Operation
Indicates summary of
operation.
Explanation of Symbols
→, ←:
(xx):
M/Q/T: Flag bits in SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
Transfer direction
Memory operand
Privilege
Indicates a
privileged
instruction.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Execution
States
Value
when no
wait states
are
inserted *
1
Sep 21, 2010
T Bit
Value of T
bit after
instruction
is executed
Explanation
of Symbols
⎯
change
: No