HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 180
![SH3-DSP, WITH USB AND LCDC, PB-F](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 3 DSP Operating Unit
Table 3.19 DC Bit Update Definitions
Page 120 of 1414
CS [2:0] Condition Mode
0 0 0 Carry or borrow
0 0 1 Negative value
0 1 0 Zero value mode
0 1 1 Overflow mode
1 0 0 Signed greater-than
1 0 1 Signed greater-or-
1 1 0 Reserved (setting prohibited)
1 1 1 Reserved (setting prohibited)
mode
mode
mode
equal mode
Description
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
When a PSHA or PSHL shift instruction is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
When an ALU or shift (PSHA) arithmetic operation is executed,
the MSB of the result, including the guard bits, is copied into the
DC bit.
When an ALU or shift (PSHL) logical operation is executed, the
MSB of the result, excluding the guard bits, is copied into the DC
bit.
The DC bit is set if the result of an ALU or shift operation is all-
zeros, and is cleared otherwise.
The DC bit is set if the result of an ALU or shift (PSHA) arithmetic
operation exceeds the destination register range, excluding the
guard bits, and is cleared otherwise.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
This mode is similar to signed greater-or-equal mode, but DC is
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
DC = 0; In case of logical operation
If the result of an ALU or shift (PSHA) arithmetic operation
exceeds the destination register range, including the guard bits
(over-range), the definition is the same as in negative value mode.
If the result is not over-range, the definition is the opposite of that
in negative value mode.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
DC = ~(negative value ^ over-range);
DC = 0 ; In case of logical operation
In case of arithmetic operation
In case of arithmetic operation
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
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