HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 807

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
22.3.9
TDFP is the write only port for transmit FIFO. Transmit FIFO has 128 stages (maximum), and can
generate interrupt of the data empty as well as of the threshold size specified by FFSZ (ACTR1).
Directly after the reset and when TE (ACTR1) bit is 0, the pointer of FIFO is set to the first
address and data becomes empty. The interrupt will occur when the TE bit (ACTR1) is written to
1 at that state. In normal case, TE bit should be changed after writing data into transmit FIFO.
22.3.10 Receive Data FIFO Port (RDFP)
RDFP is the read only register for receive FIFO. Receive FIFO has 128 stages (maximum), and
can generate interrupt of the data full as well as of the threshold size specified by FFSZ (ACTR1).
Directly after the reset and when RE bit (ACTR1) is 0, the pointer of FIFO is fixed at the first
address and data from RDFP becomes undetermined.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15 to 0
Bit
15 to 0
Transmit Data FIFO Port (TDFP)
TDFP15 to
TDFP0
RDFP15 to
RDFP0
Bit Name
Bit Name
Initial Value
All 0
Initial Value
Undefined
R/W
W
R/W
R
Description
Write only port for transmit FIFO.
Description
Read only register for receive FIFO.
Section 22 Analog Front End Interface (AFEIF)
Page 747 of 1414