HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 749

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
21.3.3
SITDR is a 32-bit write-only register that specifies the SIOF transmit data.
SITDR is initialized by the conditions specified in section 37, List of Registers, or by a transmit
reset caused by the TXRST bit in SICTR.
SITDR is initialized in module stop mode.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
31 to 16
15 to 0
Transmit Data Register (SITDR)
Bit Name
SITDL
15 to 0
SITDR
15 to 0
Initial
Value
All 0
All 0
R/W
W
W
Description
Left-Channel Transmit Data
Specify data to be output from the SIOFTxD pin as left-
channel data. The position of the left-channel data in
the transmit frame is specified by the TDLA bit in
SITDAR.
•
Right-Channel Transmit Data
Specify data to be output from the SIOFTxD pin as
right-channel data. The position of the right-channel
data in the transmit frame is specified by the TDRA bit
in SITDAR.
•
These bits are valid only when the TDLE bit in
SITDAR is set to 1.
These bits are valid only when the TDRE bit and
TLREP bit in SITDAR are set to 1 and cleared to 0,
respectively.
Section 21 Serial I/O with FIFO (SIOF)
Page 689 of 1414