HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 579

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
15 to 8 ⎯
7
6
5
4
3
2
1
0
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial
Value
All 0
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Counter Clear 2, 1, and 0
These bits select the TCNT counter clearing source.
000: TCNT clearing disabled
001: TCNT cleared by TGRA compare match
010: TCNT cleared by TGRB compare match
011: Reserved (setting prohibited)
100: TCNT clearing disabled
101: TCNT cleared by TGRC compare match
110: TCNT cleared by TGRD compare match
111: Reserved (setting prohibited)
Clock Edge 1 and 0
These bits select the input clock edge. When the input clock
is counted using both edges, the input clock period is halved
(e.g. φ/4 both edges = φ/2 rising edge). If phase counting
mode is used this setting is ignored.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges*
[Legend] X: Don't care
Note: * If Pφ/1 is selected for the input clock, operation is
Time Prescaler 2, 1, and 0
These bits select the TCNT counter clock. The clock source
can be selected independently for each channel. Table 15.3
shows the clock sources that can be set for each channel.
For more in formation on count clock selection, see table
15.4.
disabled.
Section 15 16-Bit Timer Pulse Unit (TPU)
Page 519 of 1414